Field of the Invention
The present invention relates to a nonvolatile semiconductor memory cell and to an associated semiconductor circuit configuration and an associated fabrication method, and in particular to a flash EPROM memory cell or an associated memory with a SNOR architecture, in which respective source and drain lines can be driven selectively.
In order to store relatively large volumes of data, magnetic disk drives are currently used by computer units or computers. However, such disk drives require a relatively large space and have a multiplicity of moving parts. Consequently, they are susceptible to disturbances and have a considerable current consumption. What is more, future computer units or computers and other digital devices such as, for example, digital cameras, music reproduction devices or palm devices will become smaller and smaller, which is why conventional mechanical storage devices are unsuitable.
As an alternative to such conventional mechanical storage devices, recently nonvolatile semiconductor memory devices have gained acceptance more and more, such as, for example, FLASH memories, E2PROM, EPROM and the like. The so-called NAND and NOR semiconductor memory devices are known as the most important representatives of such electrically erasable and electrically programmable memory devices. In both semiconductor memory devices, the memory cells have so-called one-transistor memory cells, usually a drain region and a source region being formed in an active region of a semiconductor substrate and an insulated charge-storing layer being situated above the channel section in between the regions.
Whereas in NAND semiconductor circuit configurations a multiplicity of switching elements are connected in series with one another and are driven via a common selection gate or a selection transistor, the respective switching elements in NOR semiconductor circuit configurations are organized in parallel or in matrix form, as a result of which each switching element can be selected individually.
What is disadvantageous, however, in the case of conventional layouts is that a more than twice as intensive metallization is present on account of the additional source lines in comparison with a xe2x80x9ccommon sourcexe2x80x9d architecture, which represents a limiting factor for more extensive integration. Therefore, conventional SNOR semiconductor memory cells usually have an area of at least 12 F2 and typically 20 F2, where F represents a smallest structure width that can be realized lithographically. What is more, so-called lithography artefacts result particularly in the case of source and drain lines of meandering configuration, and can lead to a tapering through to interruptions of the respective lines.
It is accordingly an object of the invention to provide a nonvolatile semiconductor memory cell and an associated semiconductor circuit configuration and a method for the fabricating the circuit configuration that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which further integration can be realized in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a nonvolatile semiconductor memory cell. The memory cell contains a substrate, an active region formed in the substrate and serving to define source/drain regions, a first insulating layer formed on the substrate, a charge-storing layer formed on the first insulating layer, a second insulating layer formed on the charge-storing layer, a control layer formed on the second insulating layer and defining word line stacks, an insulating protective layer surrounding at least the word line stacks, and a third insulating layer formed over a whole area on the substrate and the word line stacks. The third insulating layer has openings formed therein. At least one insulating web has sidewalls and is formed on the third insulating layer and serves to define at least one bit line with a source line and a drain line at at least one of the sidewalls. The source and drain lines each directly make contact with the source/drain regions through the openings in the third insulating layer.
In particular as a result of the use of a third insulating layer with openings above at least partial regions of the source/drain regions, and an insulating web for forming at least one bit line with a source line and a drain line at at least one of its sidewalls, the source and drain lines each directly make contact with the source/drain regions via the openings, sublithographic structure widths are obtained for the source and drain lines, as a result of which a total cell area can be reduced down to 5 F2. A storage density can be significantly increased in this way, thereby reducing the costs per memory unit.
Preferably, the source and drain lines are formed as spacers on the insulating web, thereby obtaining a structure width for the bit lines which essentially corresponds to a layer thickness for the line.
Preferably, the source and drain lines contain in situ-doped polysilicon, as a result of which the fabrication can be realized in a particularly simple manner with good conductivity.
The fourth insulating layer preferably represents a selective etching stop layer for the source and drain lines and also for the insulating web, as a result of which the fabrication method can be simplified further and the source and drain lines can be formed particularly simply and reliably. A silicon nitride layer, in particular, may advantageously be used as third insulating layer in this case, thus resulting in a high selectivity for the source and drain lines containing polysilicon and an insulating web containing TEOS oxide, for example, during etching.
An electrically conductive or electrically nonconductive layer is preferably used as the charge-storing layer.
In order to avoid so-called trench etchings in the active region, the source-drain lines and/or the openings may be formed in such a way that they overlap, thereby ensuring an improved contact connection, although at the expense of the cell size.
In accordance with an additional feature of the invention, the insulating layer is preferably formed of a tunnel oxide and the second insulating layer is formed of a coupling oxide.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a nonvolatile semiconductor memory cell and an associated semiconductor circuit configuration and a method for the fabricating the circuit configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.